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SCI Programming Model
8.6.3 SCI Clock Control Register (SCCR)
The SCCR is a read/write register that controls the selection of clock modes and baud rates for
the transmit and receive sections of the SCI interface. The SCCR is cleared by a hardware RESET
signal.
23
15
TCM
7
CD7
22
14
RCM
6
CD6
21
13
SCP
5
CD5
20
12
COD
4
CD4
19
11
CD11
3
CD3
18
10
CD10
2
CD2
17
9
CD9
1
CD1
16
8
CD8
0
CD0
Reserved. Read as 0. Write to 0 for future compatibility.
Figure 8-4. SCI Clock Control Register (SCCR)
Table 8-5. SCI Clock Control Register (SCCR) Bit Definitions
Bit
Number
23–16
15
Bit Name
TCM
Reset
Value
0
0
Description
Reserved. Write to 0 for future compatibility.
Transmit Clock Source
Selects whether an internal or external clock is used for the transmitter. If TCM is cleared,
the internal clock is used. If TCM is set, the external clock (from the SCLK signal) is used.
14
RCM
0
Receive Clock Mode Source
Selects whether an internal or external clock is used for the receiver. If RCM is cleared, the
internal clock is used. If RCM is set, the external clock (from the SCLK signal) is used.
TCM
0
0
1
1
RCM
0
1
0
1
TX Clock
Internal
Internal
External
External
RX Clock
Internal
External
Internal
External
SCLK
Output
Input
Input
Input
Mode
Synchronous/asynchronous
Asynchronous only
Asynchronous only
Synchronous/asynchronous
13
SCP
0
Clock Prescaler
Selects a divide by 1 (SCP is cleared) or divide by 8 (SCP is set) prescaler for the clock
divider. The output of the prescaler is further divided by 2 to form the SCI clock.
12
COD
0
Clock Out Divider
output is a 1 × clock.
Thus, the SCLK output is a 16 × baud clock.
The clock output divider is controlled by COD and the SCI mode. If the SCI mode is
synchronous, the output divider is fixed at divide by 2. If the SCI mode is asynchronous,
either:
? If COD is cleared and SCLK is an output (that is, TCM and RCM are both cleared), then
the SCI clock is divided by 16 before being output to the SCLK signal. Thus, the SCLK
? If COD is set and SCLK is an output, the SCI clock is fed directly out to the SCLK signal.
11–0
CD[11–0]
0
Clock Divider
Specifies the divide ratio of the prescale divider in the SCI clock generator. A divide ratio
from 1 to 4096 (CD[11–0] = $000 to $FFF) can be selected.
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
8-17
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